Multiplexers are commonly used to selectively route signals in integrated circuit devices. Many integrated circuit devices, such as field programmable gate arrays (FPGAs) and other programmable logic devices, use a relatively large number of multiplexers. FPGAs typically include a large number of multiplexers because of the large amount of replicated circuitry present in the FPGA. For example, a typical FPGA may include an array of identical configurable logic blocks (CLBs), a largely repetitive programmable interconnect structure and a plurality of identical input/output blocks (IOBs). Because one or more multiplexers are typically present in each CLB, each IOB, and each repeated segment of the programmable interconnect structure, the number of multiplexers present in the FPGA becomes quite large.
It is therefore desirable to minimize the layout area of multiplexers. It is also desirable to have a multiplexer with a regular layout shape, such that the multiplexer can be easily laid out with respect to other circuit elements of an integrated circuit. It is also desirable for a multiplexer to have a minimum delay path, such that signals transmitted through the multiplexer have a minimum associated delay.
There are many types of conventional multiplexers, one of which is described by Young in commonly assigned U.S. Pat. No. 5,744,995 [docket X-230], which is incorporated herein by reference. Other conventional multiplexers are described, for example, in U.S. Pat. Nos. 5,416,367, 4,551,634, 5,438,295, 4,692,634, 5,436,574, 5,418,480, 5,030,861, 3,614,327, and 5,570,051, all of which are incorporated herein by reference.